搜索资源列表
AlteraFPGACPLDcoder
- Altera FPGA/CPLD设计（基础篇）随书代码-Altera FPGA/CPLD design (fundamental) with the code book
AlteraFPGACPLDcoder2
- Altera FPGA/CPLD设计（高级篇）随书代码-Altera FPGA/CPLD Design (Senior Posts) With the written code
Altera_FPGA_CPLD_Designing(Advanced)
- Altera FPGA_CPLD设计(高级篇) Altera FPGA/CPLD学习的优秀参考书-Altera_FPGA_CPLD_Designing(Advanced)
Max_Plus_II-_tutorial
- Max+plusII(或写成Maxplus2,或MP2) 是Altera公司推出的的第三代PLD开发系统(Altera第四代PLD开发系统被称为：QuartusII，主要用于设计新器件和大规模CPLD/FPGA).使用MAX+PLUSII的设计者不需精通器件内部的复杂结构。设计者可以用自己熟悉的设计工具（如原理图输入或硬件描述语言）建立设计，MAX+PLUSII把这些设计转自动换成最终所需的格式。其设计速度非常快。Maxplus2被公认为是最易使用，人机界面最友善的PLD开发软件，特别适合初学者
CPLD_FPGA
- 基于CPLD/FPGA的数字通信系统建模与设计，里面讲述了通信系统的VHDL建模和各种基本电路的建模与设计，在通信原理课程设计中一般会用到！-Based on CPLD/FPGA Digital Communication System Modeling and Design, which describes VHDL modeling of communication systems and a variety of basic circuit modeling and design, pri
FPGA-CPLD
- FPGA-CPLD开发教程.rar 开发fpga必看的书籍 可以参考着开发 作为不时之需-FPGA-CPLD Development tutorial. Rar fpga development can refer to the books must see development as a rainy day
sdram_mdl
- verilog编写的对SDRAM的控制的源代码，开发FPGA/CPLD-verilog SDRAM write control of the source code, development FPGA/CPLD
CPLD--fpga
- VHDL高级应用技巧 设和深入学习VHDL者-Senior VHDL application skills and in-depth study and VHDL are based
TAXI
- 收录大量的出租车计费系统设计的资料 基于CPLD FPGA的设计抱过设计报告-Contains a large number of taxi billing information system design based on CPLD FPGA design report hug
LCD12864
- lcd12864程序，采用Verilog语言编写，在CPLD开发板上经过验证，正确无误，实现显示英文的功能，希望对大家有用-lcd12864 procedure for the Verilog language, proven in the CPLD development board, correct, implement the function displayed in English, we hope to be useful
Writing_Testbench
- 是基于CPLD/FPGA的硬件开发环境测试文本编写的优秀书籍，其语法格式更加接近于C，适合入门者使用-verilog is based on CPLD/FPGA hardware descr iption language, its syntax is closer to C, suitable for beginners to use
FPGA-CPLD-
- FPGA-CPLD-开发流程 详细的讲解开发的过程-FPGA-CPLD-development process
elecfans.com-Altera
- 利用QUATUS实现CPLD FPGA 等设计流程,书籍介绍非常详细.希望大家阅读.-Using QUATUS achieve CPLD FPGA design flow, etc., Book is very detailed. Hope you read.
cpld
- 用FPGA实现简易数字示波器，分频，触发，以及，计数-FPGA implementation using simple digital oscilloscope, frequency, trigger, and, counting
FPGA-CPLD
- FPGA/CPLD设计经验分享，数字电路设计中的经典问题分析，很实用。-FPGA/CPLD design experience sharing, digital circuit design of the classic analysis, it is practical.
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- 手把手教你学CPLD／FPGA设计（一）Taught you learn CPLD / FPGA design (a)-Taught you learn CPLD/FPGA design (a)
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- 手把手教你学CPLD／FPGA设计（二）Taught you learn CPLD / FPGA Design (B)-Taught you learn CPLD/FPGA Design (B)
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- 手把手教你学CPLD／FPGA设计（三）Taught you learn CPLD / FPGA design (c)-Taught you learn CPLD/FPGA design (c)
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- 手把手教你学CPLD／FPGA设计（四）Taught you learn CPLD / FPGA Design (D)-Taught you learn CPLD/FPGA Design (D)
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- 手把手教你学CPLD／FPGA设计（五）Taught you learn CPLD / FPGA Design (E-Taught you learn CPLD/FPGA Design (E)